Metal-insulator-semiconductor (MIS), and more specifically metal-oxide-semiconductor (MOS), capacitor memory cells are a form of dynamic memory cells. In an MIS capacitor dynamic memory cell, the information is stored in the form of the presence-vs-absence of charge in a capacitor, thereby representing a binary digital state of information. By "dynamic" is meant that the state of information in either one or the other (or both) of the two possible states tends to become degraded and ultimately to disappear with the passage of time.
An MOS capacitor memory cell can take the form of, for example, an N-type semiconductor covered with a silicon-dioxide insulator layer upon which a metal or metal-like electrical conducting plate is located. This conducting plate of the MOS capacitor is maintained at a fixed negative reference voltage while electrical writing and reading pulses are applied to the semiconductor surface portion of the capacitor (underlying the plate). A positive-going voltage or current write-in pulse, applied to the semiconductor surface portion of the MOS capacitor, injects positive charges ("hole" minority carriers) into this semiconductor substrate surface portion, thereby bringing the MOS capacitor into its binary digital "1" memory state ("full" of positive charge). On the other hand, a negative-going voltage or current write-in pulse to the semiconductor surface portion removes these positive charges out of the semiconductor substrate surface portion, thereby sharply reducing the positive charge in the semiconductor surface portion and bringing the MOS capacitor into its binary digital "0" memory state ("empty" of positive charge). However, this binary "0" state tends to become degraded with the passage of time subsequent to the negative-going write-in pulse, due to the thermal regeneration of spurious minority carriers (positively charged holes) in the N-type semiconductor substrate. This degradation takes place within the order of the semiconductor's thermal regeneration time during operation, typically of the order of a few milliseconds or less. However, even in the face of this memory degradation, a negative-going write-in voltage pulse can empty the MOS substrate surface portion of positive charges and thereby produce the binary "0" state of information for storage in the MOS capacitor at least for a short period of time; whereas, the presence of positive charges in the substrate surface portion due to a positive-going write-in pulse can produce the binary "1" for storage in the MOS capacitor.
In much of the prior art, in order to preserve the binary "0" state, the access network for reading and writing was required to devote a substantial portion of its operating time to the reading of the binary state of the capacitor only for the purpose of refreshing by re-writing the same state of the capacitor, that is, to read out and re-write even when it was not desired to read out the binary memory state of the capacitor for useful external access readout of the information stored in the MOS capacitor. This resulted in a significant loss of available access time for reading and writing, which can be an important disadvantage because system diagnostic testing consumes a substantial portion of total operating time and thus reduces this available access time, thereby putting a premium on the remaining available access time. By reason of this need for continual refreshing of the memory, not only was the memory thus not always available for external-use reading and writing, but the memory also required a substantial amount of standby power to be expended in the refresh cycles. This large expenditure of standby power arises from the fact that the entire amount of charge in the capacitor being refreshed must be removed, processed and returned during every refresh cycle. In large scale memory arrays, this standby power can thereby represent the greater portion of the total power associated with operation of the array. Moreover, in order to minimize the amount of time used for refreshing the MOS capacitor and hence increase the time available for external access reading and writing, it was necessary that the temperature of operation be kept rather low in order to decrease the required frequency of refresh by increasing the thermal regeneration time of charge carriers in the MOS capacitor, since it was the thermal regeneration of charge carriers which was responsible for the degradation and disappearance of the binary "0" state. Thus, the heat-sinking problems are rather serious especially in large scale arrays.
The detection networks for many of the prior art MOS capacitor memory cell must be able to distinguish between a fully charged cell and a cell which has been partially filled by thermally generated carriers, thereby imposing rather severe requirements on the detection margins between the two states of binary "0" and "1". Finally, many of the prior art memory cells suffer from relatively low fabrication yield for mass memory arrays, due to localized high direct-current generation sources in the silicon substrate which can render any neighboring cells inoperative after the relatively long times between successive refreshes, in turn due to the relatively low refresh frequencies used in much of the prior art, of the order of a kilocycle. Increasing the frequencies of refreshing in this prior art would, however, concomitantly increase the required power and decrease the useful operating memory time available for external access reading and writing.
In a paper entitled "A Three Transistor MOS Memory Cell with Internal Refresh," published in the 1972 IEEE International Solid-State Circuits Conference, pp. 14-15, an integrated array of dynamic memory cells is described with a mass refresh, that is, a refresh of all cells occurs by means of read and write pulses to every cell. However, this necessitates the use of a rather complex memory cell. Moreover, these read and write pulses for refresh must be turned on and applied to the cells during time intervals during which these cells are again not available for external read or write access.
In U.S. Pat. No. 3,858,184, a peripheral circuit technique for a purported automatic noninterrupting dynamic memory refresh is set forth which, however, renders the memory cells unavailable for external read or write access during the refresh pulse intervals. While this patent describes a technique for "aborting" the refresh at command of the external access; nevertheless, the time required for such "aborting" will necessarily undesirably increase the access times themselves.
In U.S. Pat. No. 3,795,898, a cross-coupled transistor static memory cell configuration is disclosed with an alternating-current (A.C.) charge pumped refresh. (By "static" memory cell is meant a memory cell in which the memory states do not become degraded with the passage of time.) However, the cross-coupled static cell is rather complex in structure. Moreover, an undesirably large amount of external standby power is required for maintaining and refreshing the memory states because, in order to get rid of a relatively small amount of spurious electrical charge, a relatively large amount of charge must be continually shifted by the A.C. pump.
Accordingly, it would be desirable to have a memory cell in which the refresh network is independent of the access reading and writing and which requires relatively low refresh standby power.